Instructions in microprocessors are often re-dispatched for execution one or more times due to pipeline errors or data hazards. For example, an instruction may need to be re-dispatched when an instruction refers to a result that has not yet been calculated or retrieved. Because it may be beneficial to uncover other independent stalls among subsequent instructions, the microprocessor may perform a runahead configured to detect other misses while the initial miss is being resolved. While runahead may uncover other potential misses, continued execution with missing or invalid data may pollute the cache.